List of signals

I just saw that you will be the mentor for this GSOC project

Indeed. It seemed appropriate as a first discussion to be initiated.

I actually dabbled a bit with nD-objects.
If you take a look at my gol project you can see an attempt to declare a 2D array of Cellular Automata (in comment). But this failed because MyHDL only descends one level into the 2D list and doesn't find all the instances. I now have a fix for this using a recursive function to go n deep.

class _HierExtr(object):

    def __init__(self, name, dut, *args, **kwargs):

        # a local subroutine
        def _nDname(top, name, obj):
                names[id(obj)] = name
                absnames[id(obj)] = "%s_%s" % (top, name)
                if isinstance(obj, (tuple, list)):
                    for i, item in enumerate(obj):
                        _nDname(top, '{}_{}'.format(name, i), item)

. . .

        for inst in hierarchy:
            obj, subs = inst.obj, inst.subs
            if id(obj) not in names:
                raise ExtractHierarchyError(_error.InconsistentHierarchy)
            inst.name = names[id(obj)]
            tn = absnames[id(obj)]
            for sn, so in subs:
                _nDname(tn, sn, so)

And I now was able to declare an [2:][2:][2:] array of RAMs:

ram_QB = [[[Signal(intbv(0)[WIDTH_D:]) for _ in range(2)] for __ in range(2)] for ___ in range(2)]
. . .
ram = [[[None for _ in range(2)] for __ in range(2)] for ___ in range(2)]
for k in range(2):
    for j in range(2):
        for i in range(2):
            ram[k][j][i] = ram2port.ram2port(NBR_COLUMNS / 2, WIDTH_D, ClkIn, wrtr_A, wrtr_Q, wra[((k*2)+j)*2+i], ClkOut, rdr_A, ram_QB[k][j][i], ADD_OUTPUT_REGISTER_B = False)